DSL service may be provided according a set of published standards including ITU-T G.992.3, ITU-T G.998.1, ITU-T G.997.1, ITU-T I.361 and ATM Forum Technical Committee “Specification of the Device Control Protocol”, Version 1.0 (af-phy-138.000) the entirety of which are expressly incorporated by reference herein.
In order to save power in DSL communication, it is desirable to switch from the normal power state L0 to the power state L2, as standardized, for example, in ITU-T 6.8/G.992.3, on the basis of bandwidth utilization.
For example, after running up in L0 mode, the DSL link may have a net data rate of NDR_L0=17 Mbit/s, which corresponds to approximately 10 asynchronous transfer mode (ATM) cells per symbol when the transmission convergence (TC) sublayer is ATM-based. In order to save as much power as possible, a low minimum L2 net data rate of 128 kbit/s may be configured.
In the L0 power state, an entity in the physical layer (PHY) or network controller (NC) measures the useful rate, and, if it is permanently below the configured 128 kbit/s, a transition to L2 is initiated. In the L2 power state, an entity in the PHY or network controller measures the bandwidth utilization, and, if this is permanently 100%, the system switches back to the L0 power state.
In practice, the output scheduler in the network controller needs to be set to the actual available net data rate, and this should be accomplished as quickly as possible. This is necessary for all online reconfigurations where the net data rate is altered, that is to say including in seamless rate adaptation (SRA). If the scheduler is not matched to a higher data rate quickly enough, a large amount of useful data becomes queued in the network controller until data may be rejected.
Further, if the useful rate is permanently below a value between NDR_L0 and NDR_L2, the L0 state is retained and no power is saved.
Still further, a useful rate in L2 permanently below NDR_L2, for example a constant bit rate (CBR) of 120 kbit/s, should not result in an L2→L0 transition.
Still further, when the useful rate in L2 rises abruptly, such as from 120 kbit/s CBR to 17 Mbit/s CBR, data need to be queued during the L2→L0 transition time (such as at 10 cells per symbol). This may result in a large number of cells no longer being able to be stored in the cell memory of the PHY when the rate monitoring is performed in the PHY and as a result a head-of-line blocking problem can arise (a particular service traffic also blocks the traffic from another service).
Although communication between PHY and NC currently takes place via the host processor of the DSL line card, the host processor manages 64 or more DSL ports, which means that the time of the information transmission is dependent on what “is currently happening on the other ports”. And even if “nothing is happening” on the other ports, such communication usually takes too long, i.e. more than 100 or even more than 1000 symbols, and, for this time, cells with a DSL-port-specific back pressure compatible interface (UTOPIA or POS-PHY) become backed up in the PHY and NC. So that the L2→L0 transition occurs quickly and few cells become backed up in the process, the rate monitoring is performed in the PHY. The rate monitoring in the PHY is currently implemented for the L2 exit to L0 over a very large time window, which is so large because an L2 useful rate below NDR_L2 must not result in an L2 exit. Since the L2 handling is performed in the PHY, the scheduler output rate in the NC is often not matched at all to the currently available PHY NDR, which means that this can result in a head-of-line blocking problem.
Moreover, the above provides no solution to the problem of L0 retention during extended periods of data rate values between NDR_L0 and NDR_L2.